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Datasheet File OCR Text:

M28W320FCT M28W320FCB
32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory
Features
Supply Voltage - VDD = 2.7V to 3.6V Core Power Supply - VDDQ= 1.65V to 3.6V for Input/Output - VPP = 12V for fast Program (optional) Access Time: 70, 80, 90, 100ns Programming Time - 10s typical - Double Word Programming Option - Quadruple Word Programming Option Common Flash Interface Memory Blocks - Parameter Blocks (Top or Bottom location) - Main Blocks Block Locking - All blocks locked at Power Up - Any combination of blocks can be locked - WP for Block Lock-Down Security - 128 bit user Programmable OTP cells - 64 bit unique device identifier Automatic Stand-by mode Program and Erase Suspend 100,000 Program/Erase cycles per block Electronic Signature - Manufacturer Code: 20h - Top Device Code, M28W320FCT: 88BAh - Bottom Device Code, M28W320FCB: 88BBh ECOPACK(R) packages
FBGA

TFBGA47 (ZB) 6.39 x 6.37mm

TSOP48 (N) 12 x 20mm

December 2007
Rev 4
1/69
www.numonyx.com 1
Contents
M28W320FCT, M28W320FCB
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 Address inputs (A0-A20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VPP Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 3.2 3.3 3.4 3.5 3.6 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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M28W320FCT, M28W320FCB
Contents
4.9 4.10 4.11 4.12 4.13 4.14 4.15
Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 5.2 5.3 5.4 5.5 Reading a Block's Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Lock-Down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . 26
6
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 VPP Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Reserved (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 8 9 10
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Contents
M28W320FCT, M28W320FCB
Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Appendix D Command interface and Program/Erase Controller state . . . . . . . 64 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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M28W320FCT, M28W320FCB
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read Block Lock Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . . 24 Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . . . 41 TFBGA47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data . . . . . 42 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Top Boot Block Addresses, M28W320FCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Bottom Boot Block Addresses, M28W320FCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Write State Machine Current/Next, sheet 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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List of figures
M28W320FCT, M28W320FCB
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . . . 41 TFBGA47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline . . 42 TFBGA47 Daisy Chain - Package Connections (Top view through package) . . . . . . . . . . 43 TFBGA47 Daisy Chain - PCB Connections proposal (Top view through package) . . . . . . 43 Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Program Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 59 Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 63
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M28W320FCT, M28W320FCB
Summary description
1
Summary description
The M28W320FCT and M28W320FCB are 32 Mbit (2 Mbit x 16) non-volatile Flash memories that can be erased electrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. VDDQ allows to drive the I/O pin down to 1.65V. An optional 12V VPP power supply is provided to speed up customer programming. The devices feature an asymmetrical blocked architecture. They have an array of 71 blocks: 8 Parameter Blocks of 4 KWord and 63 Main Blocks of 32 KWord. M28W320FCT has the Parameter Blocks at the top of the memory address space while the M28W320FCB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 4: Block Addresses. Both devices feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at Power Up. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. The device includes a Protection Register to increase the protection of a system design. The Protection Register is divided into two segments, the first is a 64 bit area which contains a unique device number written by Numonyx, while the second is a 128 bit area, one-timeprogrammable by the user. The user programmable segment can be permanently protected. Figure 5, shows the Protection Register Memory Map. Program and Erase commands are written to the Command Interface of the memory. An onchip Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The memory is offered in TSOP48 (10 X 20mm) and TFBGA47 (6.39 x 6.37mm, 0.75mm pitch) packages and is supplied with all the bits erased (set to '1'). In order to meet environmental requirements, Numonyx offers the M28W320FCT and M28W320FCB in ECOPACK(R) packages.ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
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Summary description Figure 1. Logic Diagram
VDD VDDQ VPP 21 A0-A20 W E G RP WP M28W320FCT M28W320FCB 16
M28W320FCT, M28W320FCB
DQ0-DQ15
VSS
AI09900
Table 1.
A0-A20 DQ0-DQ15 E G W RP WP VDD VDDQ VPP VSS NC
Signal Names
Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Reset Write Protect Core Power Supply Power Supply for Input/Output Optional Supply Voltage for Fast Program & Erase Ground Not Connected Internally
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M28W320FCT, M28W320FCB Figure 2. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC A20 W RP VPP WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 VDDQ VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSSQ E A0
Summary description
12 M28W320FCT 37 13 M28W320FCB 36
24
25
AI09901b
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Summary description Figure 3. TFBGA Connections (Top view through package)
1 2 3 4 5 6
M28W320FCT, M28W320FCB
7
8
A
A13
A11
A8
VPP
WP
A19
A7
A4
B
A14
A10
W
RP
A18
A17
A5
A2
C
A15
A12
A9
A20
A6
A3
A1
D
A16
DQ14
DQ5
DQ11
DQ2
DQ8
E
A0
E
VDDQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSSQ
F
VSS
DQ7
DQ13
DQ4
VDD
DQ10
DQ1
G
AI03847b
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M28W320FCT, M28W320FCB Figure 4. Block Addresses
M28W320FCT Top Boot Block Addresses
Summary description
M28W320FCB Bottom Boot Block Addresses
1FFFFF 4 KWords 1FF000 Total of 8 4 KWord Blocks 1F8FFF 4 KWords 1F8000 1F7FFF 32 KWords 1F0000
1FFFFF 32 KWords 1F8000 1F7FFF 32 KWords 1F0000 Total of 63 32 KWord Bloc
00FFFF 32 KWords 008000 007FFF 4 KWords Total of 63 32 KWord Blocks 007000 Total of 8 4 KWord Block 000FFF 32 KWords 4 KWords 000000
00FFFF 32 KWords 008000 007FFF 000000
AI09902
1. Also see Appendix A, Table 24 and Table 25 for a full listing of the Block Addresses.
Figure 5.
Protection Register Memory Map
PROTECTION REGISTER 8Ch User Programmable OTP 85h 84h Unique device number 81h 80h Protection Register Lock 2(1) 1 0
Note1. Bit 2 of the Protection Register Lock must not be programmed to 0.
AI05520
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Signal descriptions
M28W320FCT, M28W320FCB
2
Signal descriptions
See Figure 1: Logic Diagram and Figure 1: Signal Names, for a brief overview of the signals connected to this device.
2.1
Address inputs (A0-A20)
The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.
2.2
Data input/output (DQ0-DQ15)
The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level.
2.4
Output Enable (G)
The Output Enable controls data outputs during the Bus Read operation of the memory.
2.5
Write Enable (W)
The Write Enable controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first.
2.6
Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the block cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the block can be locked or unlocked. (refer to Table 7: Read Protection Register and Lock Register).
2.7
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is
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M28W320FCT, M28W320FCB
Signal descriptions
minimized. After Reset all blocks are in the Locked state. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is required to ensure valid data outputs.
2.8
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase).
2.9
VDDQ supply voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply.
2.10
VPP Program supply voltage
VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. The Supply Voltage VDD and the Program Supply Voltage VPP can be applied in any order. If VPP is kept in a low voltage range (0V to 3.6V) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see Table 15: DC Characteristics). VPP is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect on Program or Erase, however for Double or Quadruple Word Program the results are uncertain. If VPP is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed (see Table 17 and Table 18).
2.11
VSS ground
VSS is the reference for all voltage measurements. Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1F capacitor close to the pin. See Figure 7: AC Measurement Load Circuit. The PCB trace widths should be sufficient to carry the required VPP program and erase currents.
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Bus operations
M28W320FCT, M28W320FCB
3
Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2: Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.
3.1
Read
Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figure 8: Read AC Waveforms, and Table 16: Read AC Characteristics, for details of when the output becomes valid. Read mode is the default state of the device when exiting Reset or after power-up.
3.2
Write
Bus Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. See Figure 9 and Figure 10, Write AC Waveforms, and Table 17 and Table 18, Write AC Characteristics, for details of the timing requirements.
3.3
Output Disable
The data outputs are high impedance when the Output Enable is at VIH.
3.4
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable is at VIH and the device is in read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished.
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M28W320FCT, M28W320FCB
Bus operations
3.5
Automatic Standby
Automatic Standby provides a low power consumption state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, VIL, and the supply current is reduced to IDD1. The data Inputs/Outputs will still output data if a bus Read operation is in progress.
3.6
Reset
During Reset mode when Output Enable is Low, VIL, the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid.
Table 2.
Bus Operations(1)
E VIL VIL VIL VIH X G VIL VIH VIH X X W VIH VIL VIH X X RP VIH VIH VIH VIH VIL WP X X X X X VPP Don't Care VDD or VPPH Don't Care Don't Care Don't Care DQ0-DQ15 Data Output Data Input Hi-Z Hi-Z Hi-Z
Operation Bus Read Bus Write Output Disable Standby Reset
1. X = VIL or VIH, VPPH = 12V 5%.
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Command interface
M28W320FCT, M28W320FCB
4
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time during, to monitor the progress of the operation, or the Program/Erase states. See Table 3: Command Codes, for a summary of the commands and see Appendix D, and Table 32, Write State Machine Current/Next, for a summary of the Command Interface. The Command Interface is reset to Read mode when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will reset the device to Read mode. Refer to Table 4: Commands, in conjunction with the text descriptions below.
4.1
Read Memory Array command
The Read command returns the memory to its Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will read the addressed location and output the data. When a device Reset occurs, the memory defaults to Read mode.
4.2
Read Status Register command
The Status Register indicates when a program or erase operation is complete and the success or failure of the operation itself. Issue a Read Status Register command to read the Status Register's contents. Subsequent Bus Read operations read the Status Register at any address, until another command is issued. See Table 11: Status Register Bits, for details on the definitions of the bits. The Read Status Register command may be issued at any time, even during a Program/Erase operation. Any Read attempt during a Program/Erase operation will automatically output the content of the Status Register.
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M28W320FCT, M28W320FCB
Command interface
4.3
Read Electronic Signature command
The Read Electronic Signature command reads the Manufacturer and Device Codes and the Block Locking Status, or the Protection Register. The Read Electronic Signature command consists of one write cycle, a subsequent read will output the Manufacturer Code, the Device Code, the Block Lock and Lock-Down Status, or the Protection and Lock Register. See Table 5, Table 6 and Table 7 for the valid address. Table 3. Command Codes
Command Block Lock confirm Program Erase Block Lock-Down confirm Double Word Program Program Clear Status Register Reserved Quadruple Word Program Block Lock, Block Unlock, Block Lock-Down Read Status Register Read Electronic Signature Read CFI Query Program/Erase Suspend Protection Register Program Program/Erase Resume, Block Unlock confirm Read Memory Array
Hex Code 01h 10h 20h 2Fh 30h 40h 50h 55h 56h 60h 70h 90h 98h B0h C0h D0h FFh
4.4
Read CFI Query command
The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B: Common Flash Interface (CFI), Table 26, Table 27, Table 28, Table 29, Table 30 and Table 31 for details on the information contained in the Common Flash Interface memory area.
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Command interface
M28W320FCT, M28W320FCB
4.5
Block Erase command
The Block Erase command can be used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. 1. 2. The first bus cycle sets up the Erase command. The second latches the block address in the internal state machine and starts the Program/Erase Controller.
If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. During Erase operations the memory will accept the Read Status Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table 8: Program, Erase Times and Program/Erase Endurance Cycles. See Appendix C, Figure 20: Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Erase command.
4.6
Program command
The memory array can be programmed word-by-word. Two bus write cycles are required to issue the Program Command. 1. 2. The first bus cycle sets up the Program command. The second latches the Address and the Data to be written and starts the Program/Erase Controller.
During Program operations the memory will accept the Read Status Register command and the Program/Erase Suspend command. Typical Program times are given in Table 8: Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 16: Program Flowchart and Pseudo Code, for the flowchart for using the Program command.
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M28W320FCT, M28W320FCB
Command interface
4.7
Double Word Program command
This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when VPP is not at VPPH. Three bus write cycles are necessary to issue the Double Word Program command. 1. 2. 3. The first bus cycle sets up the Double Word Program Command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 17: Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program command.
4.8
Quadruple Word Program command
This feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel.The four words must differ only for the addresses A0 and A1. Programming should not be attempted when VPP is not at VPPH. Five bus write cycles are necessary to issue the Quadruple Word Program command. 1. 2. 3. 4. 5. The first bus cycle sets up the Quadruple Word Program Command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written. The fourth bus cycle latches the Address and the Data of the third word to be written. The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 18: Quadruple Word Program Flowchart and Pseudo Code, for the flowchart for using the Quadruple Word Program command.
4.9
Clear Status Register command
The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One bus write cycle is required to issue the Clear Status Register command. The bits in the Status Register do not automatically return to `0' when a new Program or Erase command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command.
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Command interface
M28W320FCT, M28W320FCB
4.10
Program/Erase Suspend command
The Program/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program, Double Word Program, Quadruple Word Program, Block Lock, Block Lock-Down or Protection Program commands will also be accepted. The block being erased may be protected by issuing the Block Protect, Block Lock or Protection Program commands. When the Program/Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or programmed correctly. During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 19: Program Suspend & Resume Flowchart and Pseudo Code, and Figure 21: Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Suspend command.
4.11
Program/Erase Resume command
The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the command. Once the command is issued subsequent Bus Read operations read the Status Register. See Appendix C, Figure 19: Program Suspend & Resume Flowchart and Pseudo Code, and Figure 21: Erase Suspend & Resume Flowchart and Pseudo Code, and Figure 21: Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Resume command.
4.12
Protection Register Program command
The Protection Register Program command is used to Program the 128 bit user One-TimeProgrammable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Two write cycles are required to issue the Protection Register Program command. 1. 2. The first bus cycle sets up the Protection Register Program command. The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure 5: Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register is not reversible. The Protection Register Program cannot be suspended.
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Command interface
4.13
Block Lock command
The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. 1. 2. The first bus cycle sets up the Block Lock command. The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature command. Table 10 shows the protection status after issuing a Block Lock command. The Block Lock bits are volatile, once set they remain set until a hardware reset or powerdown/power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation.
4.14
Block Unlock command
The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command. 1. 2. The first bus cycle sets up the Block Unlock command. The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature command. Table 10 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation.
4.15
Block Lock-Down command
A locked block cannot be Programmed or Erased, or have its protection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command. 1. 2. The first bus cycle sets up the Block Lock command. The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 10 shows the protection status after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation.
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Command interface Table 4. Commands(1)(2)
Bus Write Operations Commands Cycles 1st Cycle Op Read Memory Array Read Status Register Read Electronic Signature Read CFI Query Erase Program Double Word Program(4) Quadruple Word Program(5) Clear Status Register Program/Erase Suspend Program/Erase Resume Block Lock Block Unlock Block Lock-Down Protection Register Program 1+ Write 1+ Write 1+ Write 1+ Write 2 2 Write Write Add X X X X X X Data FFh 70h 90h 98h 20h 40h or 10h 30h 56h
(6)
M28W320FCT, M28W320FCB
2nd Cycle Op Read Read Read Read Write Write Add Data RA X SA
(3)
3rd Cycle Op Add Data Op
4th Cycle Add Data Op
5th Cycle Add Data
RD SRD IDh QD D0h PD
QA BA PA
3 5 1 1 1 2 2 2 2
Write Write Write Write Write Write Write Write Write
X X X X X X X X X
Write Write
PA1 PA1
PD1 PD1
Write Write
PA2 PA2
PD2 PD2 Write PA3 PD3 Write PA4 PD4
50h B0h D0h 60h 60h 60h C0h Write Write Write BA BA BA 01h D0h 2Fh
Write PRA PRD
1. X = Don't Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device Code), QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data. 2. 55h is reserved. 3. The signature addresses are listed in Table 5, Table 6 and Table 7. 4. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0. 5. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1. 6. To be characterized.
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M28W320FCT, M28W320FCB Table 5.
Code Manufacture. Code M28W320FCT Device Code M28W320FCB
1. RP = VIH.
Command interface
Read Electronic Signature(1)
Device E VIL VIL VIL G VIL VIL VIL W VIH VIH VIH A0 VIL VIH VIH A1 VIL VIL VIL A2-A7 0 0 0 A8-A20 Don't Care Don't Care Don't Care DQ0-DQ7 20h BAh BBh DQ8-DQ15 00h 88h 88h
Table 6.
Read Block Lock Signature
E VIL VIL VIL G VIL VIL VIL W VIH VIH VIH A0 VIL VIL VIL A1 VIH VIH VIH A2-A7 0 0 0 A8-A11 A12-A20 DQ0 1 0 X(1) DQ1 0 0 1 DQ2-DQ15 00h 00h 00h
Block Status Locked Block Unlocked Block Locked-Down Block
Don't Care Block Address Don't Care Block Address Don't Care Block Address
1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section.
Table 7.
Word
Read Protection Register and Lock Register
E G W A0A7 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch A8-A20 DQ0 DQ1 OTP Prot. data ID data ID data ID data ID data OTP data OTP data OTP data OTP data OTP data OTP data OTP data OTP data DQ2 Don't Care See note(1) ID data ID data ID data ID data OTP data OTP data OTP data OTP data OTP data OTP data OTP data OTP data DQ3DQ7 Don't Care ID data ID data ID data ID data OTP data OTP data OTP data OTP data OTP data OTP data OTP data OTP data DQ8DQ15 Don't Care ID data ID data ID data ID data OTP data OTP data OTP data OTP data OTP data OTP data OTP data OTP data
Lock Unique ID 0 Unique ID 1 Unique ID 2 Unique ID 3 OTP 0 OTP 1 OTP 2 OTP 3 OTP 4 OTP 5 OTP 6 OTP 7
VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL
VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL
VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH
Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care
Don't Care ID data ID data ID data ID data OTP data OTP data OTP data OTP data OTP data OTP data OTP data OTP data
1. DQ2 in the Protection Lock Register must not be programmed to 0.
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Command interface Table 8.
M28W320FCT, M28W320FCB
Program, Erase Times and Program/Erase Endurance Cycles
M28W320FCT, M28W320FCB Parameter Test Conditions Min Typ 10 10 10 0.16/0.08 0.32 0.02/0.01 0.04 1 1 0.4 0.4 100,000 20
(1) (1)
Unit Max 200 200 200 5 5 4 4 10 10 10 10 s s s s s s s s s s s cycles years
Word Program Double Word Program Quadruple Word Program Main Block Program
VPP = VDD VPP = 12V 5% VPP = 12V 5% VPP = 12V 5% VPP = VDD
Parameter Block Program
VPP = 12V 5% VPP = VDD
Main Block Erase
VPP = 12V 5% VPP = VDD
Parameter Block Erase Program/Erase Cycles (per Block) Data Retention
VPP = 12V 5% VPP = VDD
1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple Word Program commands respectively.
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M28W320FCT, M28W320FCB
Block locking
5
Block locking
The M28W320FCT and M28W320FCB feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection.

Lock/Unlock - this first level allows software-only control of block locking. Lock-Down - this second level requires hardware interaction before locking can be changed. VPP VPPLK - the third level offers a complete hardware protection against program and erase on all blocks.
The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 10 defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 22, shows a flowchart for the locking operations.
5.1
Reading a Block's Lock Status
The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 6, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system.
5.2
Locked state
The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command.
5.3
Unlocked state
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powereddown. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command.
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Block locking
M28W320FCT, M28W320FCB
5.4
Lock-Down state
Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. Locked-Down blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (VIH) the Lock-Down function is disabled (1,1,1) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be locked again (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is low, blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was high. Device reset or power-down resets all blocks, including those in Lock-Down, to the Locked state.
5.5
Locking operations during Erase Suspend
Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix D: Command interface and Program/Erase Controller state, for detailed information on which commands are valid during erase suspend. Table 9. Block Lock Status
Item Block Lock Configuration Block is Unlocked xx002 Block is Locked Block is Locked-Down DQ0=1 DQ1=1 Address Data LOCK DQ0=0
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M28W320FCT, M28W320FCB Table 10. Protection Status
Next Protection Status(1) (WP, DQ1, DQ0) After Block Lock Command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 After Block Unlock Command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-Down Command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1 (WP, DQ1, DQ0) Program/Erase Allowed yes no yes no yes no no
Block locking
Current Protection Status(1)
Current State
After WP transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0 (3)
1,0,0 1,0,1(2) 1,1,0 1,1,1 0,0,0 0,0,1(2) 0,1,1
1. The lock status is defined by the write protect pin and by DQ1 (`1' for a locked-down block) and DQ0 (`1' for a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
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Status Register
M28W320FCT, M28W320FCB
6
Status Register
The Status Register provides information on the current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read Status Register command can be issued, refer to Read Status Register Command section. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to VIH. Either Chip Enable or Output Enable must be toggled to update the latched data. Bus Read operations from any address always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 11: Status Register Bits. Refer to Table 11 in conjunction with the following text descriptions.
6.1
Program/Erase Controller Status (Bit 7)
The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During Program, Erase, operations the Program/Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Lock Status bits should be tested for errors.
6.2
Erase Suspend Status (Bit 6)
The Erase Suspend Status bit indicates that an Erase operation has been suspended or is going to be suspended. When the Erase Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 7 is set within 30s of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low.
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M28W320FCT, M28W320FCB
Status Register
6.3
Erase Status (Bit 5)
The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.
6.4
Program Status (Bit 4)
The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.
6.5
VPP Status (Bit 3)
The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage; when the VPP Status bit is High (set to `1'), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed. Once set High, the VPP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.
6.6
Program Suspend Status (Bit 2)
The Program Suspend Status bit indicates that a Program operation has been suspended. When the Program Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 2 is set within 5s of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low.
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Status Register
M28W320FCT, M28W320FCB
6.7
Block Protection Status (Bit 1)
The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to `1'), a Program or Erase operation has been attempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.
6.8
Reserved (Bit 0)
Bit 0 of the Status Register is reserved. Its value must be masked. Note: Refer to Appendix C: Flowcharts and pseudo codes, for using the Status Register.
Table 11.
Bit 7
Status Register Bits
Name P/E.C. Status '0' '1' Busy Suspended In progress or Completed Erase Error Erase Success Program Error Program Success VPP Invalid, Abort VPP OK Suspended In Progress or Completed Program/Erase on protected Block, Abort No operation to protected blocks Logic Level (1) '1' Ready Definition
6
Erase Suspend Status '0' '1'
5
Erase Status '0' '1'
4
Program Status '0' '1'
3
VPP Status
'0' '1'
2
Program Suspend Status '0' '1'
1 0
Block Protection Status '0' Reserved
1. Logic level '1' is High, '0' is Low.
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M28W320FCT, M28W320FCB
Maximum rating
7
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 12.
Symbol TA TBIAS TSTG VIO VDD, VDDQ VPP
Absolute Maximum Ratings
Value Parameter Min Ambient Operating Temperature(1) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage - 40 - 40 - 55 - 0.6 - 0.6 - 0.6 Max 85 125 155 VDDQ+0.6 4.1 13 C C C V V V Unit
1. Depends on range.
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DC and AC parameters
M28W320FCT, M28W320FCB
8
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table : . Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 13.
Operating and AC Measurement Conditions
M28W320FCT, M28W320FCB
Parameter Min VDD Supply Voltage VDDQ Supply Voltage (VDDQ VDD) Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 2.7 2.7 - 40
70 Max 3.6 3.6 85 50 5 0 to VDDQ VDDQ/2 Min 2.7 2.7 - 40
85 Max 3.6 3.6 85 50 5 0 to VDDQ VDDQ/2 Min 2.7 2.7 - 40
90 Max 3.6 3.6 85 50 5 0 to VDDQ VDDQ/2 Min 2.7 1.65 - 40
10 Units Max 3.6 3.6 85 50 5 0 to VDDQ VDDQ/2 V V C pF ns V V
Figure 6.
AC Measurement I/O Waveform
VDDQ VDDQ/2 0V
AI00610
32/69
M28W320FCT, M28W320FCB Figure 7. AC Measurement Load Circuit
VDDQ
DC and AC parameters
VDDQ VDD 25k DEVICE UNDER TEST 0.1F 0.1F CL 25k
CL includes JIG capacitance
AI00609C
Table 14.
Symbol CIN COUT
Capacitance(1)
Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
1. Sampled only, not 100% tested.
Table 15.
Symbol ILI ILO IDD IDD1 IDD2
DC Characteristics
Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Stand-by or Automatic Stand-by) Supply Current (Reset) Test Condition 0VVIN VDDQ 0V VOUT DDQ V E = VSS, G = VIH, f = 5MHz E = VDDQ 0.2V, RP = VDDQ 0.2V RP = VSS 0.2V Program in progress VPP = 12V 5% Program in progress VPP = VDD Erase in progress VPP = 12V 5% Erase in progress VPP = VDD Supply Current (Program/Erase Suspend) Program Current (Read or Stand-by) E = VDDQ 0.2V, Erase suspended VPP > VDD 9 15 15 5 10 5 10 15 Min Typ Max 1 10 18 50 50 10 20 20 20 50 400 Unit A A mA A A mA mA mA mA A A
IDD3
Supply Current (Program)
IDD4
Supply Current (Erase)
IDD5 IPP
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DC and AC parameters Table 15.
Symbol IPP1 IPP2
M28W320FCT, M28W320FCB
DC Characteristics (continued)
Parameter Program Current (Read or Stand-by) Program Current (Reset) Test Condition VPP VDD RP = VSS 0.2V Program in progress VPP = 12V 5% Program in progress VPP = VDD Erase in progress VPP = 12V 5% Erase in progress VPP = VDD -0.5 Input Low Voltage VDDQ 2.7V VDDQ 2.7V IOL = 100A, VDD = VDD min, VDDQ = VDDQ min IOH = -100A, VDD = VDD min, VDDQ -0.1 VDDQ = VDDQ min 1.65 3.6 Min Typ 1 1 1 1 3 1 Max 5 5 10 5 10 5 0.4 0.8 VDDQ +0.4 VDDQ +0.4 0.1 Unit A A mA A mA A V V V V V V V
IPP3
Program Current (Program)
IPP4
Program Current (Erase)
VIL
-0.5 VDDQ -0.4 0.7 VDDQ
VIH VOL VOH VPP1
Input High Voltage
Output Low Voltage Output High Voltage Program Voltage (Program or Erase operations) Program Voltage (Program or Erase operations) Program Voltage (Program and Erase lockout) VDD Supply Voltage (Program and Erase lockout)
VPPH
11.4
12.6
V
VPPLK
1
V
VLKO
2
V
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M28W320FCT, M28W320FCB Figure 8. Read AC Waveforms
tAVAV A0-A20 tAVQV E tELQV tELQX G tGLQV tGLQX DQ0-DQ15 VALID VALID
DC and AC parameters
tAXQX
tEHQX tEHQZ
tGHQX tGHQZ
ADDR. VALID CHIP ENABLE
OUTPUTS ENABLED
DATA VALID
STANDBY
AI02688b
Table 16.
Symbol tAVAV tAVQV tAXQX(1) tEHQX(1) tEHQZ(1) tELQV(2) tELQX(1) tGHQX(1) tGHQZ(1) tGLQV(2) tGLQX(1)
Read AC Characteristics
M28W320FCT, M28W320FCB Alt tRC Parameter 70 Address Valid to Next Address Valid Min Max Min Min Max Max Min Min Max Max Min 70 70 0 0 20 70 0 0 20 20 0 85 85 85 0 0 20 85 0 0 20 20 0 90 90 90 0 0 25 90 0 0 25 30 0 10 100 100 0 0 30 100 0 0 30 35 0 ns ns ns ns ns ns ns ns ns ns ns Unit
tACC Address Valid to Output Valid tOH tOH tHZ tCE tLZ tOH tDF tOE Address Transition to Output Transition Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid
tOLZ Output Enable Low to Output Transition
1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
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PROGRAM OR ERASE tAVAV VALID tAVWH tWHAX tWHEH tWHWL tWHGL tWLWH tWHEL tWHDX COMMAND CMD or DATA STATUS REGISTER tELQV
Figure 9.
DC and AC parameters
A0-A20
E
tELWL
G
W
tDVWH
Write AC Waveforms, Write Enable Controlled
DQ0-DQ15
tWPHWH
tQVWPL
WP
tVPHWH
tQVVPL
VPP
SET-UP COMMAND
CONFIRM COMMAND OR DATA INPUT
STATUS REGISTER READ 1st POLLING
AI03574b
M28W320FCT, M28W320FCB
M28W320FCT, M28W320FCB Table 17.
Symbol tAVAV tAVWH tDVWH tELWL tELQV tQVVPL
(1)(2)
DC and AC parameters
Write AC Characteristics, Write Enable Controlled
M28W320FCT, M28W320FCB Alt tWC tAS tDS tCS Write Cycle Time Address Valid to Write Enable High Data Valid to Write Enable High Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Output Valid to VPP Low Output Valid to Write Protect Low tVPS VPP High to Write Enable High tAH tDH tCH Write Enable High to Address Transition Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Output Enable Low tWPH Write Enable High to Write Enable Low tWP Write Enable Low to Write Enable High Write Protect High to Write Enable High Parameter 70 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70 45 45 0 70 0 0 200 0 0 0 25 20 25 45 45 85 85 45 45 0 85 0 0 200 0 0 0 25 20 25 45 45 90 90 50 50 0 90 0 0 200 0 0 0 30 30 30 50 50 10 100 50 50 0 100 0 0 200 0 0 0 30 30 30 50 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tQVWPL tVPHWH
(1)
tWHAX tWHDX tWHEH tWHEL tWHGL tWHWL tWLWH tWPHWH
1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
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PROGRAM OR ERASE tAVAV VALID tAVEH tEHAX tEHWH tEHEL tEHGL tELEH tEHDX COMMAND tWPHEH CMD or DATA STATUS REGISTER tQVWPL tELQV tVPHEH tQVVPL CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI03575b
DC and AC parameters
A0-A20
W
tWLEL
G
E
tDVEH
Figure 10. Write AC Waveforms, Chip Enable Controlled
DQ0-DQ15
WP
VPP
M28W320FCT, M28W320FCB
POWER-UP AND SET-UP COMMAND
M28W320FCT, M28W320FCB Table 18.
Symbol tAVAV tAVEH tDVEH tEHAX tEHDX tEHEL tEHGL tEHWH tELEH tELQV tQVVPL
(2) (1)
DC and AC parameters
Write AC Characteristics, Chip Enable Controlled
M28W320FCT, M28W320FCB Alt tWC tAS tDS tAH tDH Write Cycle Time Address Valid to Chip Enable High Data Valid to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Data Transition Parameter 70 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70 45 45 0 0 25 25 0 45 70 0 0 200 0 45 85 85 45 45 0 0 25 25 0 45 85 0 0 200 0 45 90 90 50 50 0 0 30 30 0 50 90 0 0 200 0 50 10 100 50 50 0 0 30 30 0 50 100 0 0 200 0 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tCPH Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low tWH tCP Chip Enable High to Write Enable High Chip Enable Low to Chip Enable High Chip Enable Low to Output Valid Output Valid to VPP Low Data Valid to Write Protect Low tVPS VPP High to Chip Enable High tCS Write Enable Low to Chip Enable Low Write Protect High to Chip Enable High
tQVWPL tVPHEH(1) tWLEL tWPHEH
1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
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DC and AC parameters Figure 11. Power-Up and Reset AC Waveforms
M28W320FCT, M28W320FCB
W, E, G
tPHWL tPHEL tPHGL
tPHWL tPHEL tPHGL
RP tVDHPH VDD, VDDQ Power-Up Reset
AI03537b
tPLPH
Table 19.
Symbol
Power-Up and Reset AC Characteristics
M28W320FCT, M28W320FCB Parameter Test Condition 70 85 50 30 100 50 90 50 30 100 50 10 50 30 100 50 s ns ns s During Program and Erase others Unit
tPHWL tPHEL tPHGL
Reset High to Write Enable Low, Chip Enable Low, Output Enable Low
Min Min Min Min
50 30 100 50
tPLPH(1)(2) Reset Low to Reset High tVDHPH
(3)
Supply Voltages High to Reset High
1. The device Reset is possible but not guaranteed if tPLPH < 100ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.
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M28W320FCT, M28W320FCB
Package mechanical
9
Package mechanical
Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
1. Drawing is not to scale.
Table 20.
Symbol
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
mm Typ Min Max 1.20 0.05 0.95 0.17 0.10 19.80 18.30 11.90 0.50 - 0.50 0 48 0.10 0.15 1.05 0.27 0.21 20.20 18.50 12.10 - 0.70 5 0.0197 0.0020 0.0374 0.0067 0.0039 0.7795 0.7205 0.4685 - 0.0197 0 48 0.0039 Typ inches Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.7953 0.7283 0.4764 - 0.0279 5
A A1 A2 B C D D1 E e L N CP
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Package mechanical
M28W320FCT, M28W320FCB
Figure 13. TFBGA47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline
D FD FE D1 SD
SE E E1 e ddd
BALL "A1" e A A1 b A2
BGA-Z35
1. Drawing is not to scale.
Table 21.
Symbol
TFBGA47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data
millimeters Typ Min Max 1.200 0.200 1.000 0.400 6.390 5.250 0.350 6.290 - 0.450 6.490 - 0.100 6.370 3.750 0.750 0.570 1.310 0.375 0.375 6.270 - - - - - - 6.470 - - - - - - 0.2508 0.1476 0.0295 0.0224 0.0516 0.0148 0.0148 0.2469 - - - - - - 0.0157 0.2516 0.2067 0.0138 0.2476 - 0.0079 0.0394 0.0177 0.2555 - 0.0039 0.2547 - - - - - - Typ inches Min Max 0.0472
A A1 A2 b D D1 ddd E E1 e FD FE SD SE
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M28W320FCT, M28W320FCB
Package mechanical
Figure 14. TFBGA47 Daisy Chain - Package Connections (Top view through package)
1 2 3 4 5 6 7 8
A
B
C
D
E
F
AI03295
Figure 15. TFBGA47 Daisy Chain - PCB Connections proposal (Top view through package)
1 2 3 4 5 6 7 8
A
START POINT
B
C
D
E
F
END POINT
AI03296
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Part numbering
M28W320FCT, M28W320FCB
10
Part numbering
Table 22.
Example:
Ordering Information Scheme
M28W320FCT 70 N 6 E
Device Type M28
Operating Voltage W = VDD = 2.7V to 3.6V; VDDQ = 1.65V to 3.6V
Device Function 320FC = 32 Mbit (2 Mb x16), Boot Block
Array Matrix T = Top Boot B = Bottom Boot
Speed 70 = 70ns 85 = 85ns 90 = 90ns 10 = 100ns
Package N = TSOP48: 12 x 20mm ZB = TFBGA47: 6.39 x 6.37mm, 0.75 mm pitch
Temperature Range 6 = -40 to 85 C
Option E = ECOPACK Package, Standard Packing F = ECOPACK Package, Tape & Reel 24mm Packing
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M28W320FCT, M28W320FCB Table 23. Daisy Chain Ordering Scheme
-ZB E
Part numbering
Example:M28W320FC
Device Type M28W320FC
Daisy Chain -ZB = TFBGA47: 6.39 x 6.37mm, 0.75 mm pitch
Option E = ECOPACK Package, Standard Packing F = ECOPACK Package, Tape & Reel 24mm Packing
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you.
45/69
Block address tables
M28W320FCT, M28W320FCB
Appendix A
Table 24.
Block address tables
Top Boot Block Addresses, M28W320FCT
# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1FF000-1FFFFF 1FE000-1FEFFF 1FD000-1FDFFF 1FC000-1FCFFF 1FB000-1FBFFF 1FA000-1FAFFF 1F9000-1F9FFF 1F8000-1F8FFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF
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M28W320FCT, M28W320FCB Table 24.
Block address tables
Top Boot Block Addresses, M28W320FCT (continued)
# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F00000-F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF
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Block address tables Table 24.
M28W320FCT, M28W320FCB Top Boot Block Addresses, M28W320FCT (continued)
# 67 68 69 Size (KWord) 32 32 32 Address Range 018000-01FFFF 010000-017FFF 008000-00FFFF
Table 25.
Bottom Boot Block Addresses, M28W320FCB
# 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF
48/69
M28W320FCT, M28W320FCB Table 25.
Block address tables
Bottom Boot Block Addresses, M28W320FCB (continued)
# 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 Address Range 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 007000-007FFF
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Block address tables Table 25.
M28W320FCT, M28W320FCB Bottom Boot Block Addresses, M28W320FCB (continued)
# 6 5 4 3 2 1 Size (KWord) 4 4 4 4 4 4 Address Range 006000-006FFF 005000-005FFF 004000-004FFF 003000-003FFF 002000-002FFF 001000-001FFF
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M28W320FCT, M28W320FCB
Common Flash Interface (CFI)
Appendix B
Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the data structure is read from the memory. Table 26, Table 27, Table 28, Table 29, Table 30 and Table 31 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 31: Security Code Area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Issue a Read command to return to Read mode. Table 26.
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table
Query Structure Overview(1)
Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional)
1. Query data are always presented on the lowest order data outputs.
Table 27.
Offset 00h 01h
CFI Query Identification String(1)
Data 0020h 88BAh 88BBh Manufacturer Code Device Code Description Value Numonyx Top Bottom
02h-0Fh reserved Reserved 10h 11h 12h 13h 14h 15h 16h 0051h 0052h 0059h 0003h 0000h 0035h Address for Primary Algorithm extended Query table (see Table 29) 0000h P = 35h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Query Unique ASCII String "QRY" "Q" "R" "Y" Intel compatible
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Common Flash Interface (CFI) Table 27.
Offset 17h 18h 19h 1Ah
M28W320FCT, M28W320FCB
CFI Query Identification String(1) (continued)
Data 0000h 0000h 0000h 0000h Description Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (0000h means none exists) Address for Alternate Algorithm extended Query table (0000h means none exists) Value NA
NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.
Table 28.
Offset
CFI Query System Interface Information
Data Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV Typical time-out per single word program = 2n s Typical time-out for Double/ Quadruple Word Program = 2 s Typical time-out per individual block erase = 2 ms Typical time-out for full chip erase = 2n ms Maximum time-out for word program = 2 times typical Maximum time-out for Double/ Quadruple Word Program = 2 times typical Maximum time-out per individual block erase = 2n times typical
n n n n
Value
1Bh
0027h
2.7V
1Ch
0036h
3.6V
1Dh
00B4h
11.4V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
00C6h 0004h 0004h 000Ah 0000h 0005h 0005h 0003h 0000h
12.6V 16s 16s 1s NA 512s 512s 8s NA
Maximum time-out for chip erase = 2n times typical
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M28W320FCT, M28W320FCB Table 29.
Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh M28W320FCT 2Fh 30h 31h 32h 33h 34h 2Dh 2Eh M28W320FCB 2Fh 30h 31h 32h 33h 34h
Common Flash Interface (CFI)
Device Geometry Definition
Data 0016h 0001h 0000h 0003h 0000h 0002h 003Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within the device. It specifies the number of regions within the device containing contiguous Erase Blocks of the same size. Region 1 Information Number of identical-size erase block = 003Eh+1 Region 1 Information Block size in Region 1 = 0100h * 256 byte Region 2 Information Number of identical-size erase block = 0007h+1 Region 2 Information Block size in Region 2 = 0020h * 256 byte Region 1 Information Number of identical-size erase block = 0007h+1 Region 1 Information Block size in Region 1 = 0020h * 256 byte Region 2 Information Number of identical-size erase block = 003Eh=1 Region 2 Information Block size in Region 2 = 0100h * 256 byte Value 4 MByte x16 Async. 8
2
63 64 KByte 8 8 KByte 8 8 KByte 63 64 KByte
53/69
Common Flash Interface (CFI) Table 30.
Offset P = 35h (1) (P+0)h = 35h (P+1)h = 36h (P+2)h = 37h (P+3)h = 38h (P+4)h = 39h (P+5)h = 3Ah (P+6)h = 3Bh (P+7)h = 3Ch
M28W320FCT, M28W320FCB
Primary Algorithm-Specific Extended Query Table
Data 0050h 0052h 0049h 0031h 0030h 0066h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. bit 0Chip Erase supported(1 = Yes, 0 = No) bit 1Suspend Erase supported(1 = Yes, 0 = No) bit 2Suspend Program supported(1 = Yes, 0 = No) bit 3Legacy Lock/Unlock supported(1 = Yes, 0 = No) bit 4Queued Erase supported(1 = Yes, 0 = No) bit 5Instant individual block locking supported(1 = Yes, 0 = No) bit 6Protection bits supported(1 = Yes, 0 = No) bit 7Page mode read supported(1 = Yes, 0 = No) bit 8Synchronous read supported(1 = Yes, 0 = No) bit 31 to 9Reserved; undefined bits are `0' Supported Functions after Suspend Read Array, Read Status Register and CFI Query are always supported during Erase or Program operation bit 0Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1Reserved; undefined bits are `0' Block Lock Status Defines which bits in the Block Status Register section of the Query are implemented. Address (P+A)h contains less significant byte bit 0Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No) bit 1Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2Reserved for future use; undefined bits are `0' VDD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV VPP Supply Optimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Primary Algorithm extended Query table unique ASCII string "PRI" Description Value "P" "R" "I" "1" "0"
(P+8)h = 3Dh
0000h
No Yes Yes No No Yes Yes No No
(P+9)h = 3Eh
0001h
Yes
(P+A)h = 3Fh
0003h
(P+B)h = 40h
0000h
Yes Yes
(P+C)h = 41h
0030h
3V
(P+D)h = 42h
00C0h
12V
(P+E)h = 43h
0001h
01
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M28W320FCT, M28W320FCB Table 30.
Offset P = 35h (1) (P+F)h = 44h (P+10)h = 45h (P+11)h = 46h
Common Flash Interface (CFI)
Primary Algorithm-Specific Extended Query Table
Data 0080h 0000h 0003h Description Protection Field 1: Protection Description This field describes user-available. One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with device unique serial numbers. Others are user programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bit 0 to 7 Lock/bytes JEDEC-plane physical low address bit 8 to 15Lock/bytes JEDEC-plane physical high address bit 16 to 23 "n" such that 2n = factory pre-programmed bytes bit 24 to 31 "n" such that 2n = user programmable bytes Reserved Value 80h 00h 8 Byte
(P+12)h = 47h
0003h
8 Byte
(P+13)h = 48h
1. See Table 27, offset 15 for P pointer definition.
Table 31.
Offset 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch
Security Code Area
Data 00XX XXXX XXXX 64 bits: unique device number XXXX XXXX XXXX XXXX XXXX XXXX 128 bits: User Programmable OTP XXXX XXXX XXXX XXXX Protection Register Lock Description
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Flowcharts and pseudo codes
M28W320FCT, M28W320FCB
Appendix C
Flowcharts and pseudo codes
Figure 16. Program Flowchart and Pseudo Code
Start
Write 40h or 10h
program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10) ; */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Write Address & Data
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI03538b
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
56/69
M28W320FCT, M28W320FCB Figure 17. Double Word Program Flowchart and Pseudo Code
Flowcharts and pseudo codes
Start
Write 30h
Write Address 1 & Data 1 (3)
Write Address 2 & Data 2 (3)
double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (any_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI03539b
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
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Flowcharts and pseudo codes Figure 18. Quadruple Word Program Flowchart and Pseudo Code
Start
M28W320FCT, M28W320FCB
Write 56h
Write Address 1 & Data 1 (3)
quadruple_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { writeToFlash (any_address, 0x56) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */
Write Address 2 & Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ writeToFlash (addressToProgram3, dataToProgram3) ; /*see note (3) */ writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */
Write Address 3 & Data 3 (3)
Write Address 4 & Data 4 (3)
/*Memory enters read status state after the Program command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06233
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
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M28W320FCT, M28W320FCB
Flowcharts and pseudo codes
Figure 19. Program Suspend & Resume Flowchart and Pseudo Code
Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Write B0h
Read Status Register
b7 = 1 YES b2 = 1 YES Write FFh
NO
} while (status_register.b7== 0) ;
NO
Program Complete
if (status_register.b2==0) /*program completed */ { writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another address
} else { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } } Read Data
Write D0h
Write FFh
Program Continues
AI03540b
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Flowcharts and pseudo codes Figure 20. Erase Flowchart and Pseudo Code
M28W320FCT, M28W320FCB
Start erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ; writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */
Write 20h
Write Block Address & D0h
Read Status Register
do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
b7 = 1
NO } while (status_register.b7== 0) ;
YES b3 = 0 YES b4, b5 = 1 NO b5 = 0 YES b1 = 0 YES End }
AI03541b
NO
VPP Invalid Error (1)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
YES
Command Sequence Error (1)
if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ;
NO
Erase Error (1)
if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ;
NO
Erase to Protected Block Error (1)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
60/69
M28W320FCT, M28W320FCB
Flowcharts and pseudo codes
Figure 21. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
erase_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
b7 = 1 YES b6 = 1 YES Write FFh
NO
} while (status_register.b7== 0) ;
NO
Erase Complete
if (status_register.b6==0) /*erase completed */ { writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock else
} { writeToFlash (any_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase*/ } }
Write D0h
Write FFh
Erase Continues
Read Data
AI03542b
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Flowcharts and pseudo codes Figure 22. Locking Operations Flowchart and Pseudo Code
M28W320FCT, M28W320FCB
Start
Write 60h
locking_operation_command (address, lock_operation) { writeToFlash (any_address, 0x60) ; /*configuration setup*/ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (any_address, 0x90) ;
Write 01h, D0h or 2Fh
Write 90h
Read Block Lock States
Locking change confirmed? YES Write FFh
NO
if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/
writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/ }
End
AI04364
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M28W320FCT, M28W320FCB
Flowcharts and pseudo codes
Figure 23. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h
protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ;
Write Address & Data
writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI04381
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
63/69
Command interface and Program/Erase Controller state
M28W320FCT, M28W320FCB
Appendix D
Command interface and Program/Erase Controller state
Table 32.
Write State Machine Current/Next, sheet 1 of 2.(1)
Command Input (and Next State) SR bit 7 Data When Read
Current State
Read Array (FFh) Read Array Read Array Read Array Read Array
Program Setup (10/40h) Prog. Setup Program Setup Program Setup Program Setup
Erase Setup (20h) Ers. Setup Erase Setup Erase Setup Erase Setup
Erase Confirm (D0h)
Prog/Ers Suspend (B0h) Read Array Read Array Read Array Read Array
Prog/Ers Resume (D0h)
Read Status (70h) Read Sts. Read Sts Read Sts Read Sts
Clear Status (50h) Read Array Read Array Read Array Read Array
Read Array Read Status Read Elect.Sg. Read CFI Query Lock Setup Lock Cmd Error Lock (complete) Prot. Prog. Setup Prot. Prog. (continue) Prot. Prog. (complete) Prog. Setup Program (continue) Prog. Sus Status Prog. Sus Read Array Prog. Sus Read Elect.Sg. Prog. Sus Read CFI Program (complete)
"1" "1" "1" "1" "1" "1" "1" "1" "0" "1" "1" "0"
Array Status Electronic Signature CFI Status Status Status Status Status Status Status Status
Lock Command Error Read Array Read Array Program Setup Program Setup Erase Setup Erase Setup
Lock Lock Cmd (complete) Error Read Array Read Array
Lock Lock Command Error (complete) Read Sts Read Sts Read Array Read Array
Protection Register Program Protection Register Program continue Read Array Program Setup Erase Setup Read Array Program Program (continue) Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Read Array Program Suspend to Read Array Program Suspend to Read Array Program Suspend to Read Array Program Suspend to Read Array Program Setup Erase Setup Program (continue) Program (continue) Program (continue) Program (continue) Prog. Sus Read Sts Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Prog. Sus Read Array Read Array Program (continue) Program (continue) Program (continue) Program (continue) Program (continue) Prog. Sus Prog. Read Sus Array Read Sts Prog. Sus Prog. Read Sus Array Read Sts Prog. Prog. Sus Sus Read Read Sts Array Prog. Sus Prog. Read Sus Array Read Sts Read Sts Read Array Read Sts Read Array
"1"
Status
"1"
Array
"1"
Electronic Signature
"1"
CFI
"1"
Status
64/69
M28W320FCT, M28W320FCB Table 32.
Command interface and Program/Erase Controller state
Write State Machine Current/Next, sheet 1 of 2.(1) (continued)
Command Input (and Next State) SR bit 7 Data When Read
Current State
Read Array (FFh)
Program Setup (10/40h)
Erase Setup (20h)
Erase Confirm (D0h) Erase (continue)
Prog/Ers Suspend (B0h) Erase CmdError Read Array Erase Sus Read Sts
Prog/Ers Resume (D0h) Erase (continue)
Read Status (70h)
Clear Status (50h)
Erase Setup Erase Cmd.Error Erase (continue) Erase Sus Read Sts Erase Sus Read Array Erase Sus Read Elect.Sg. Erase Sus Read CFI Erase (complete)
"1" "1" "0"
Status Status Status
Erase Command Error Read Array Program Setup Erase Setup
Erase Command Error Read Sts Read Array
Erase (continue) Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Read Array Program Setup Program Setup Program Setup Program Setup Program Setup Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Erase Setup Erase (continue) Erase (continue) Erase (continue) Erase (continue)
Erase (continue) Erase (continue) Erase (continue) Erase (continue) Erase (continue) Erase Erase Sus Read Sus Array Read Sts Erase Erase Sus Read Sus Array Read Sts Erase Erase Sus Read Sus Read Sts Array Erase Erase Sus Read Sus Array Read Sts Read Sts Read Array
"1"
Status
Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Erase Sus Read Array Read Array
"1"
Array
"1"
Electronic Signature
"1"
CFI
"1"
Status
1. Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.
65/69
Command interface and Program/Erase Controller state Table 33. Write State Machine Current/Next, sheet 2 of 2 (1)
Command Input (and Next State) Current State Read Elect.Sg. (90h) Read Array Read Status Read Elect.Sg. Read CFI Query Lock Setup Lock Cmd Error Lock (complete) Prot. Prog. Setup Prot. Prog. (continue) Prot. Prog. (complete) Prog. Setup Program (continue) Prog. Suspend Read Status Prog. Suspend Read Elect.Sg. Prog. Suspend Read Elect.Sg. Prog. Suspend Read Elect.Sg. Prog. Suspend Read Elect.Sg. Read Elect.Sg. Prog. Suspend Read CFI Query Prog. Suspend Read CFI Query Prog. Suspend Read CFI Query Prog. Suspend Read CFI Query Read CFIQuery Lock Setup Read Elect.Sg. Read CFI Query Read Elect.Sg. Read Elect.Sg. Read Elect.Sg. Read Elect.Sg. Read Elect.Sg. Read Elect.Sg. Read CFI Query (98h) Read CFI Query Read CFI Query Read CFI Query Read CFI Query Lock Setup (60h) Prot. Prog. Setup (C0h) Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup
M28W320FCT, M28W320FCB
Lock Confirm (01h)
Lock Down Confirm (2Fh) Read Array Read Array Read Array Read Array Lock (complete)
Unlock Confirm (D0h)
Lock Setup Lock Setup Lock Setup Lock Setup
Lock Command Error Read CFI Query Read CFI Query Lock Setup Lock Setup Prot. Prog. Setup Prot. Prog. Setup
Read Array Read Array
Protection Register Program Protection Register Program (continue) Lock Setup Prot. Prog. Setup Program Program (continue) Read Array
Program Suspend Read Array
Program (continue)
Prog. Suspend Read Array
Program Suspend Read Array
Program (continue)
Prog. Suspend Read Elect.Sg.
Program Suspend Read Array
Program (continue)
Prog. Suspend Read CFI Program (complete) Erase Setup Erase Cmd.Error
Program Suspend Read Array
Program (continue)
Prot. Prog. Setup
Read Array Erase (continue) Read Array
Erase Command Error Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Setup
66/69
M28W320FCT, M28W320FCB Table 33.
Command interface and Program/Erase Controller state
Write State Machine Current/Next, sheet 2 of 2 (continued)(1)
Command Input (and Next State)
Current State
Read Elect.Sg. (90h)
Read CFI Query (98h)
Lock Setup (60h)
Prot. Prog. Setup (C0h)
Lock Confirm (01h)
Lock Down Confirm (2Fh)
Unlock Confirm (D0h)
Erase (continue) Erase Suspend Read Ststus Erase Suspend Read Array Erase Suspend Read Elect.Sg. Erase Suspend Read CFI Query Erase (complete) Erase Suspend Read Elect.Sg. Erase Suspend Read Elect.Sg. Erase Suspend Read Elect.Sg. Erase Suspend Read Elect.Sg. Read Elect.Sg. Erase Suspend Read CFI Query Erase Suspend Read CFI Query Erase Suspend Read CFI Query Erase Suspend Read CFI Query Read CFI Query
Erase (continue)
Lock Setup
Erase Suspend Read Array
Erase (continue)
Lock Setup
Erase Suspend Read Array
Erase (continue)
Lock Setup
Erase Suspend Read Array
Erase (continue)
Lock Setup
Erase Suspend Read Array
Erase (continue)
Lock Setup
Prot. Prog. Setup
Read Array
1. Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.
67/69
Revision history
M28W320FCT, M28W320FCB
11
Revision history
Table 34.
Date 24-May-2004 23-Aug-2004
Document revision history
Revision 0.1 0.2 First Issue Figure 2: TSOP Connections and Figure 3: TFBGA Connections (Top view through package). Datasheet status promoted to Full Datasheet. 85, 90 and 100ns speed classes removed. Temperature range 1 (0 to 70C) removed. Leaded package options removed and ECOPACK text updated. 85, 90 and 100ns access time added. Table 13: Operating and AC Measurement Conditions, Table 16: Read AC Characteristics, Table 17: Write AC Characteristics, Write Enable Controlled, Table 18: Write AC Characteristics, Chip Enable Controlled, and Table 19: Power-Up and Reset AC Characteristics updated. Table 22: Ordering Information Scheme modified. Device function updated in Table 22: Ordering Information Scheme to remove the 0.13m technology. Applied Numonyx branding. Changes
12-Jul-2005
1.0
28-Mar-2006
2
16-Oct-2006 10-Dec-2007
3 4
68/69
M28W320FCT, M28W320FCB
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